Blog
Ramblings on technology, life and unicorns
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CTNet - compressing neural networks with video codecs
Can h.265 compress network parameters?
Posted in ctnet, machine-learning, compression
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CUBED - 144 Forth processors in your browser
An in-browser emulator for the GreenArrays GA144 with a twist.
Posted in cubed, fpga, programming-languages
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emudrama and interpersonal relationships: a retrospective
A public retrospective on the Reicast/Flycast and FEX-Emu/hex-emu dramas.
Posted in emulators, personal
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Another Code Cache approach for hex-emu (fex-emu derivative/fork)
Multi-threaded, multi-process JIT object code cache for hex-emu with BST index and crash safety.
Posted in FEX-Emu, emulators
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Dreamcast Emulation on PS2?
Thought experiment on running Dreamcast emulation on the PS2 hardware.
Posted in emulators, nullDC
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Implementing an AOT pipeline for FEX-Emu
Ahead-of-time IR caching that cuts clang launch time from 1.3s to 0.38s under FEX-Emu.
Posted in FEX-Emu, emulators
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Getting started with FPGAdc and HLS, part 1
First steps implementing the Dreamcast's CLX2 CORE rendering unit in HLS for FPGA.
Posted in fpgadc, emulators
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Full interview with NullDC/Reicast developers (skmp, ZNullptr)
An in-depth interview covering the history of NullDC and Reicast, the Dreamcast emulation scene, and the technical journey behind these projects.
Posted in interviews, emulators
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Running Anbox on Raspberry Pi
Step-by-step guide to running Android apps on Raspberry Pi 4 via Anbox.
Posted in linux, android
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Micro optimizations & emulation
How fixing pointer aliasing, signed modulo, and using SSE/AVX intrinsics yielded a 32% speedup in reicast's TA processing.
Posted in reicast, emulators
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Efficiently handling endian differences using negative memory addressing
A novel technique for handling endian conversion in emulators using negative memory offsets.
Posted in emulators
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Updated Reicast CI builds page
Redesigned the Reicast automated builds page with jquery, underscorejs and regex.
Posted in reicast
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reicast, websockets & opengl (es) streaming
Streaming Dreamcast rendering over websockets using glReadPixels and WebGL.
Posted in reicast, emulators
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Tegra K1: First impression
First reicast test on NVIDIA Jetson TK1 - amazing Dreamcast emulation performance.
Posted in reicast, emulators
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Simple SoC 16: Wait States
Add wait states for ICE & module integration on the CPU. Have it talk nicely with the debugger.
Posted in hsgr, fpga, verilog
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Simple SoC 15: Debugger Integration
ICE state machine implementation, got it talking with the debugger - VGA writes working!
Posted in hsgr, fpga, verilog
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Simple SoC 14: Making it work once more
Get the modularised code back into working state. Implement some of the ICE state machine.
Posted in hsgr, fpga, verilog
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Simple SoC 13: ICEful modules
Modularization and refactoring of the SoC codebase.
Posted in hsgr, fpga, verilog
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Simple SoC 12: Debuggable Hardware
Work on the ICE implementation.
Posted in hsgr, fpga, verilog
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Simple SoC 11: Clocks and IO
Worked around the IO/DCM issues. WIP on the ICE implementation.
Posted in hsgr, fpga, verilog
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Simple SoC 10: Want some ICE?
Almost implemented UART. Ran into pin collisions on clock vs DCM vs IO-standards per bank.
Posted in hsgr, fpga, verilog
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Simple SoC 9: Differential debugging
Investigate serial communications, try out UART sample, draft out ICE spec.
Posted in hsgr, fpga, verilog
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Simple SoC 8: Corrupted Pixels
No luck locating the VGA corruption bug - simulator results and simpler test cases work fine. Implemented wait.
Posted in hsgr, fpga, verilog
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Simple SoC 7: We love glitches
Fixed VGA, centered image - still outputs corrupted data though. VRAM resized to 256x256x3 to fit.
Posted in hsgr, fpga, verilog
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Simple SoC 6: How about conditions?
Implemented beq, bga, bgt, jr, draw, fixed write16/read16. Wired up VRAM and added VGA output - glitchy but alive.
Posted in hsgr, fpga, verilog
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Simple SoC 5: Howdy Simulator, for real
Debug, debug, debug, and simulate. Implemented more state logic - CPU mostly works, needs some more opcodes.
Posted in hsgr, fpga, verilog
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Simple SoC 4: Howdy Simulator
Implemented RAM and added delays for RAM.
Posted in hsgr, fpga, verilog
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Simple SoC 3: Verilog at last
Spec now has vsync, reviewed sdlcore code, hacked together some very basic Verilog.
Posted in hsgr, fpga, verilog
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Simple SoC 2: Let there be code
Debugged and finished the sdlcore implementation.
Posted in hsgr, fpga, verilog
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Simple SoC 1: September reunion
Discuss and improve specs, update documentation and C# reference implementation. Forked from Programmable Logic Lessons.
Posted in hsgr, fpga, verilog
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PLD Workshop 6: Computer architecture, part 3
Brainstorming the final CPU design, porting to Verilog, and assembler implementation, at hackerspace.gr.
Posted in hsgr, fpga, verilog
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PLD Workshop 5: Computer architecture, part 2
ISA design - ALU, branching, registers, load/store. Pipeline stages and ISA implementation, at hackerspace.gr.
Posted in hsgr, fpga, verilog
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PLD Workshop 4: Computer architecture
Introduction to computer architecture - buses, ALU, registers, instruction sets. Teams implement a basic CPU in C/C++, at hackerspace.gr.
Posted in hsgr, fpga, verilog
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PLD Workshop 3: More complicated structures
Clocked vs asynchronous design, clock dividers, clock domains, buffers, FIFOs, and pipelines, at hackerspace.gr.
Posted in hsgr, fpga, verilog
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PLD Workshop 2: Tooling, VHDL/Verilog basics
Xilinx tooling, VHDL & Verilog introduction - design goals, history, syntax, and hands-on basics, at hackerspace.gr.
Posted in hsgr, fpga, verilog
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PLD Workshop 1: Digital electronics recap
Fast recap of digital electronics basics - binary system, logic gates, combinational and sequential circuits, at hackerspace.gr.
Posted in hsgr, fpga, verilog
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quick update
ndce compiles with psl1ght, but no 3D output yet.
Posted in Uncategorized
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ports, ports & ports !
ARM code-path ported to Android, dynamic code running on PS3.
Posted in Uncategorized
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Resuming operations !
Back to coding after a break - nullDCe on Android, PPC rec improvements for Wii.
Posted in nullDC, ps3
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Progess
nullDCe showing first visuals on PS3 - main menu and VMUs working.
Posted in emulators, nullDC, ps3
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Progress on ps3: toolchain / basic open source sdk is the next target ...
Basic cross compile of nulldce core working on PS3, now targeting open toolchain.
Posted in emulators, nullDC, ps3
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Resuming work on nullDC ! -- also, donations needed :|
Officially back to working on nullDC, with plans for PS3 and Xbox ports.
Posted in emulators, nullDC, ps3
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Some habits are too hard to break, huh
nullDC dynarec instrumentation and profiling results for Shenmue.
Posted in emulators, nullDC
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nullDC mainline is open source ! also, moved servers :)
nullDC mainline code released as open source on Google Code.
Posted in nullDC
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Finaly some progress !
New dynarec with IL, backends for x86/arm/mips-allegrex, and first PSP/BeagleBoard results.
Posted in Uncategorized
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Clarifications about nullDC/psp
Setting expectations about nullDC/psp development, speed, and future ports.
Posted in nullDC, nullDC/psp
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nullDC/PSP update #2++
GDrom support added, DOA2LE and SOTB running on PSP.
Posted in nullDC, nullDC/psp