Getting started with FPGAdc and HLS, part 1

I’ve been meaning to work on an fpga implementation of the Dreamcast for almost 2 years now, and last week finally I have an ultra96 I can play with.

Current idea is to move CLX2’s CORE into a memory mapped device, then once that is working, to add the TA component, and offload all of the rendering to the fpga, while the rest of the Dreamcast runs emulated.

What’s what?

• HLS - High Level Synthesis, essentially a C/C++ to hdl (verilog/vhdl) compiler.
• CLX2 - The PowerVR part used in the Dreamcast
• CORE - The pixel rendering unit of CLX2. Reads command lists and renders to an on chip tile buffer.
• TA - The “Tile Accelerator” unit of CLX2. Gets polygons and prepares commands lists for CORE.
• ISP - The “Image Synthesis Processor”, determines which pixels are visible
• TSP - The “Texture and Shading Processor”, calculates pixel color

First steps

Getting started with fpga dev is always frustrating. I decided to “cheat” and try HLS using Vivado HLS. While the HLS path is no substitute for hand-written hdl code, I already have a clean C-based implementation in reicast that I can quickly port.

Getting the code to compile for HLS

I had to refactor the code to be more “hardware friendly”:

• Getting rid of unions and replacing them with bitmath
• Getting rid of pointers, replacing with global indexes to global arrays
• Making template parameters function arguments
• Implementing a memory-mapped interface

Show me the pixels

Initial ISP results looked like this:

After implementing multiple triangle support and adding the TSP module:

Then hooked into reicast:

Keep in mind, this is still running as C code, and not in the FPGA fabric.

But will it fit?

TL;DR answer: Maybe, Vivado HLS thinks so. I was told not to trust this too much before I see it running.

There’s quite a bit more work left to do — synthesizing the verilog, connecting over AXI, getting linux and reicast running on the board. That’s all for now ~