SH4 Pipeline Simulator
A work-in-progress web-based simulator for the Hitachi SH4 processor’s instruction pipeline — the CPU at the heart of the Sega Dreamcast. Visualizes serial and parallel execution, instruction latency, flow/output/anti-flow dependencies, resource conflicts on floating-point operations, stage locks, and stall cycles.
Covers instruction scheduling scenarios for FADD, FMOV, FIPR, FTRV, and other SH4 operations.